The present invention relates to a circuit for detecting signals present on a bifilar voltage-supply and signal-transmission line in which the signals are constituted by positive and negative variations of the supply potential of at least one of the wires of the line.
Digital signal detection circuits are used, for example in a digital-data communication system with an ASI (actuator-sensor interface) field bus and, more precisely, in the data-receiving stage. An ASI communication system serves for the remote control of sensors and actuators in the industrial automation field.
FIG. 1 of the appended drawings shows the main components of an ASI communication system. Transmission takes place on a bus constituted by a bifilar line 2 which also serves for the supply of the entire system. A voltage supply 3 is connected to the line by means of a decoupling device 4. As shown in FIG. 2, a positive potential V+, for example +15V, and a negative potential Vxe2x88x92, for example xe2x88x9215V, relative to a reference terminal indicated by the ground symbol in FIG. 2, are applied to the two wires of the line, respectively. The decoupling device 4 comprises two inductors L, for example, of 50 xcexcH, each in parallel with a resistor R, for example, of 39 ohms, on a respective one of the two wires of the line.
A supervision (master) unit 5 and various subservient (slave) units 6 are connected to the line. The master unit 5 contains a central controller and transmission and receiving members for controlling data communication and the management of the system by means of a suitable interface. Each slave unit 6 contains members for transmitting, receiving, and processing the data to be sent on the line 2 or to be taken therefrom and is connected to sensors and actuators 7. The transmission members generate signals that are applied to the line as variations of the supply potentials V+ and Vxe2x88x92 of the two wires by alternating pulse modulation (APM), and that are transmitted on the line in series.
FIG. 3 shows, in the form of graphs (a) to (g), how the APM modulation takes place and how the signal is transmitted and reconstructed. Graph (a) indicates a sequence of bits to be transmitted, graph (b) shows the same sequence encoded in accordance with the Manchester code (switching, at the center of the bit time, downwards for a bit equal to 0 and upwards for a bit equal to 1), and graph (c) shows the corresponding current signal sent by the transmission member on the line. For each change in current, the line responds, for each wire, with a voltage pulse (positive if the current changes from a maximum level Im to 0 and negative if the current changes from 0 to Im).
As shown in graphs (d1) and (d2), the potential of each of the wires is constituted by the superimposition of the supply potential V+ and Vxe2x88x92 and the variation v in potential, for example xc2x11V, due to the signal. Each wire carries the whole signal, represented by potentials of opposite sign. With this type of modulation, the polarities of two successive pulses are always opposite. The signal is decoded by reading the polarities of the pulses at intervals equal to one bit time (for example 6 xcexcs). In particular, if the pulse is positive, the datum read is logic 1 and vice versa. Graphs (e) and (f) show two square-wave sequences corresponding, respectively, to negative pulses and to positive pulses of the signal present on the positive wire of the line, that is, the line with the supply potential V+. Graph (g) shows the bit sequence reconstructed in accordance with the Manchester code.
A known circuit for detecting the voltage pulses on the two wires of the transmission line is shown in a block diagram in FIG. 4. The ASI+ and ASIxe2x88x92 signal present on the wires of the line 2 is amplified in an amplifier 10 and discriminated by two diodes 11a and 11b. A detection path for the positive pulse and a detection path for the negative path are thus formed. In each of the two paths, the signal is passed through a band-pass filter 12a, 12b and then detected by a threshold comparator 13a, 13b. The thresholds of the comparators are fixed at the value of the continuous component of the voltage at the output of the amplifier 10 derived, for example, by a sample-and-hold circuit 14 the operation of which is synchronized by a clock signal CLK. The outputs of the two comparators thus supply the positive sequence and the negative sequence of the signal which are then processed in a sequence-control circuit 15 in order to reconstruct the digital signal transmitted and to eliminate any errors introduced in transmission.
The known circuit described above is quite complex and requires the use of a synchronization signal.
The present invention provides a digital signal detection circuit that performs signal detection in a manner that is simpler than the signal detection performed by prior art detection circuits and does not require a synchronization signal.